Routing issues in Nanometer-scale . . .

As integrated circuits (ICs) have scaled into nanometer dimensions, operating at gigahertz frequencies, interconnects have become critical in determining system performance, reliability, and manufacturability. This thesis presents new algorithms dealing with several important aspects of VLSI interconnects optimization and prediction, namely, noise reduction in global routing, temperature-aware global routing for three-dimensional (3D) ICs, buffer insertions issues for global interconnects in structured ASICs, and chemical mechanical polishing (CMP)-aware routing for optimized dummy metal fills. The issue of crosstalk noise during global routing is first targeted in this work, employing both buffers and shielding lines to mitigate this noise. A dynamic programming-like algorithm is utilized to efficiently reduce crosstalk noise under the constraints of routing and buffering resources. The algorithm is presented under a flexible supply network architecture so that existing power wires are utilized as shields. The noise level is evaluated with the simple yet effective metric proposed by Devgan. It is proposed that Devgan’s metric, which is pessimistic and is known to have limited accuracy, shows excellent fidelity properties, and a noise margin inflation technique is developed to compensate for its pessimism. The second issue studied in this thesis is related to electrothermally-conscious global routing for 3D ICs. 3D ICs are built by stacking multiple layers of active devices, which provides the potential for reduced interconnect delays. However, this technology is plagued with thermal problems. Our global routing algorithm, in addition to solving the routing problem in all three dimensions, plans thermal vias and thermal wires to establish good heat conduction paths. The algorithm utilizes sensitivity analysis and linear programming techniques to judiciously allocate the usage of thermal vias and thermal wires, and iteratively resolve contentions between signal routing, thermal vias and thermal wires, while simultaneously managing thermal tradeoffs. The next part of the thesis considers buffering global interconnects in structured ASICs. This is a relatively new technology that creates extremely regular layouts, primarily in order to avoid a